VLSI: Difference between revisions
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From Verilog/VHDL to GDSII |
From Verilog/VHDL to GDSII |
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for SKY or IHP technologies. |
for SKY or IHP technologies. |
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* [[LibreLane]] (superseeding OpenLane) has its own page here. |
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* [[OpenLane 2]] (going obsolete) has its own wiki page here |
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= Prerequisites = |
= Prerequisites = |
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* KLayout - viewer and editor of GDSII files |
* KLayout - viewer and editor of GDSII files |
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* OpenRoad - Automates floorplanning, placement, routing and timing. |
* OpenRoad - Automates floorplanning, placement, routing and timing. |
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* OpenLane - Automated design flow, from verilog to GDSII, uses the tools above. |
* OpenLane - (obsolete) Automated design flow, from verilog to GDSII, uses the tools above. |
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* LibreLane - superseeds the OpenLane. |
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== Open Technology PDKs == |
== Open Technology PDKs == |
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Process development kits (PDK) available for OSS VLSI: |
Process development kits (PDK) available for OSS VLSI: |
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* SKY 130 PDK - Process Design Kit by Google and Efabless |
* '''SKY 130 PDK''' - Process Design Kit by Google and Efabless |
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** [https://github.com/google/skywater-pdk GitHub repo] |
** [https://github.com/google/skywater-pdk GitHub repo] |
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** [https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html ReadTheDocs] |
** [https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html ReadTheDocs] |
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** [https://www.skywatertechnology.com/sky130-open-source-pdk/ Description at SkywaterTechnology, 2023] |
** [https://www.skywatertechnology.com/sky130-open-source-pdk/ Description at SkywaterTechnology, 2023] |
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* [https://www.ihp-microelectronics.com/services/research-and-prototyping-service/fast-design-enablement/open-source-pdk IHP PDK] |
* [https://www.ihp-microelectronics.com/services/research-and-prototyping-service/fast-design-enablement/open-source-pdk '''IHP SG13G2 PDK'''] |
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** This is a 130nm BiCMOS process from the Leibniz Institute for High Performance Microelectronics, which generally offers higher performance (faster transitions) than Sky130. |
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** Open Source PDK in 130nm BiCMOS, developed for Analog/Digital, Mixed Signal and RF ASIC Design |
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** [https://ihp-open-pdk-docs.readthedocs.io/en/latest/ ReadTheDocs] |
** [https://ihp-open-pdk-docs.readthedocs.io/en/latest/ ReadTheDocs] |
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Other, less popular options: |
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= Setup Openline2 = |
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The advised path is to setup NIX envbironment and then run openline from there, rather than using a dockerized version. |
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= Usecase: Simple counter = |
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* GlobalFoundries 180nm MCU (GF180MCU) |
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= Usecase: RAM integration = |
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** A mature 180nm CMOS process with 5 layers of metal, widely used for analog and mixed-signal design. It is fully supported by Efabless for open-source shuttle programs. |
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TODO. |
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* ASAP7 (Arizona State Academic Process) |
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= Usecase: NeoRV32 MCU = |
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** A 7nm predictive PDK used exclusively for academic research and educational purposes. It is often used for evaluating next-generation PnR flows (e.g., using Synopsys tools). |
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* SCMOS (Scalable CMOS) |
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** An older "Lambda-based" design rule set used before modern open foundry efforts, helpful for learning layout concepts, though not used for modern, high-performance silicon fabrication. |
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== Tapeout == |
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NeoRV32 is an open source MCU with many peripheral options written in VHDL. |
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[https:// |
[https://tinytapeout.com/ TinyTapeout: from idea/design to chip/PCB] |
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* [https://app.tinytapeout.com/calculator?tiles=1&pcbs=1&shuttle=chipfoundry TinyTapeout calculator] |
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Latest revision as of 19:57, 3 July 2026
Open source VLSI design notes.
From Verilog/VHDL to GDSII for SKY or IHP technologies.
- LibreLane (superseeding OpenLane) has its own page here.
- OpenLane 2 (going obsolete) has its own wiki page here
Prerequisites
These notes assume the host has Linux, e.g. Ubuntu 24.04 set up. All tools will be running under it.
Open Tools
Essential OSS HW design tools
- gtkwave - Waveform viewer
- iverilog - Icarus Verilog compiler
- Verilator - compile RTL to C++, faster simulations
- Yosys - RTL to gate level netlist
- SymbiFlow - Toolchain to FPGA
- Magic VLSI - transistor level layout design editor
- KLayout - viewer and editor of GDSII files
- OpenRoad - Automates floorplanning, placement, routing and timing.
- OpenLane - (obsolete) Automated design flow, from verilog to GDSII, uses the tools above.
- LibreLane - superseeds the OpenLane.
Open Technology PDKs
Process development kits (PDK) available for OSS VLSI:
- SKY 130 PDK - Process Design Kit by Google and Efabless
- IHP SG13G2 PDK
- This is a 130nm BiCMOS process from the Leibniz Institute for High Performance Microelectronics, which generally offers higher performance (faster transitions) than Sky130.
- ReadTheDocs
Other, less popular options:
- GlobalFoundries 180nm MCU (GF180MCU)
- A mature 180nm CMOS process with 5 layers of metal, widely used for analog and mixed-signal design. It is fully supported by Efabless for open-source shuttle programs.
- ASAP7 (Arizona State Academic Process)
- A 7nm predictive PDK used exclusively for academic research and educational purposes. It is often used for evaluating next-generation PnR flows (e.g., using Synopsys tools).
- SCMOS (Scalable CMOS)
- An older "Lambda-based" design rule set used before modern open foundry efforts, helpful for learning layout concepts, though not used for modern, high-performance silicon fabrication.