Difference between revisions of "LU-DIP-B10:index"

Latest revision as of 16:46, 17 December 2010

Ievads digitālajā projektēšanā

LU DF kurss, bakalaura programma, 2010.g rudens

Kursa apraksts: [LV], [EN]

Pasniedzējs: Artis Mednis

Notiek: piektdienās, 8:30 - 12:10

Ziņu kopa: lu-dip-b pie googlegroups punkts com

Lai pievienotos ziņu kopai, lūdzu sūtīt e-pastu pasniedzējam: artis punkts mednis pie gmail punkts com

Kalendārs

Nedēļas datumi	Kursa saturs
30.08.2010 - 05.09.2010	Reģistrācijas nedēļa
10.09.2010	Ievadlekcija. Digitālās projektēšanas process. Praktiskais darbs PD1. Mājas darbs MD1, termiņš 17.09.2010 08:30
17.09.2010	Digitālo iekārtu izstrādes pamatelementi. Xilinx Spartan 3E. Praktiskais darbs PD2. Mājas darbs MD2, termiņš 24.09.2010 08:30
24.09.2010	Trigeri. Pulkstenis. Praktiskais darbs PD3. Mājas darbs MD3, termiņš 01.10.2010 08:30
01.10.2010	CPU. DataPath. ALU. Praktiskais darbs PD4. Mājas darbs MD4, termiņš 08.10.2010 08:30
08.10.2010	CPU. DataPath (turpinājums). Instrukciju izpildes maģistrāle. Praktiskais darbs PD5. Kursa projekts KP1, termiņš 1. daļai - 15.10.2010 12:10, 2. daļai - 22.10.2010 12:10
15.10.2010	CPU. DataPath (turpinājums). Zarošanās. Kontrole. Praktiskajos darbos turpinām strādāt pie kursa projekta KP1.
22.10.2010	CPU. DataPath (nobeigums). Ātrāks summators. Reģistru fails. Praktiskajos darbos turpinām strādāt pie kursa projekta KP1.
29.10.2010	09:00 Vidus semestra kontroldarbs Kursa projekts KP2, termiņš - 12.11.2010 12:10
05.11.2010	DLX procesors un instrukcijas. Praktiskajos darbos turpinām strādāt pie kursa projekta KP2.
12.11.2010	Aparatūras apraksta valodas. Verilog. Praktiskajos darbos turpinām strādāt pie kursa projekta KP2.
13.11.2010	Aparatūras apraksta valodas. VHDL. Kursa projekts KP3, termiņš specifikācijai - 26.11.2010, visam projektam - 14.01.2011
26.11.2010	Atmiņa. Fiziskās realizācijas varianti. Praktiskajos darbos turpinām strādāt pie kursa projekta KP3.
03.12.2010	Daudztaktu procesors. Praktiskajos darbos turpinām strādāt pie kursa projekta KP3. Multicycle CPU PDF 455.60KB (lekciju slaidi no Case Western Reserve University)
10.12.2010	Daudztaktu procesors (nobeigums). Praktiskajos darbos turpinām strādāt pie kursa projekta KP3. Designing a Pipelined CPU PDF 116.22KB (lekciju slaidi no San Diego Supercomputer Center)
17.12.2010	FPGA. Praktiskajos darbos turpinām strādāt pie kursa projekta KP3. How Does FPGA Work PDF 1.06MB (lekciju slaidi no Lund University)
24.12.2010 - 02.01.2011	Ziemassvētku un Jaungada brīvdienas
07.01.2011	08:30 - 12:10 Konsultācijas
14.01.2011	09:30 - 10:15 Gala eksāmena kontroldarbs
14.01.2011	10:30 - 11:15 Projektu prezentācijas - kursa noslēgums

Praktiskie darbi (PD)

Mājas darbi (MD)

Kursa projekti (KP)

Literatūra

Computer organization and design: the hardware/software interface
- Computer Organization & Design The Hardware/Software Interface, 2nd Edition PPT 5.89MB (lekciju slaidi no National Chiao Tung University)
- Computer Organization & Design The Hardware/Software Interface, 3nd Edition PPT 1.86MB (lekciju slaidi no National Chiao Tung University)

Computer architecture: a quantitative approach

The designer's guide to VHDL

Saites

Xilinx kompānijas (FPGA ražotājs) portāls

Digital design textbooks @ Digilent Inc.

Introduction to Digital Design - Verilog Edition PDF 5.81MB
Introduction to Digital Design - VHDL Edition PDF 6.68MB
Real Digital - A hands-on approach to digital design
- Module 1: Introduction to Electronic Circuits PDF 465.54KB
- Module 2: Introduction to Digilent's Digital Design Circuit Boards PDF 65.94KB
- Module 3: Circuit Structure with an Introduction to CAD Tools PDF 247.60KB
- Module 4: Logic Minimization PDF 353.07KB
- Module 5: Introduction to VHDL PDF 197.37KB
- Module 6: Combinational Circuit Blocks PDF 244.46KB
- Module 7: Combinational Arithmetic Circuits PDF 361.00KB
- Module 8: Signal Propagation Delays PDF 126.77KB
- Module 9: Basic Memory Circuits PDF 232.41KB
- Module 10: The Structural Design of Sequential Circuits PDF 245.58KB

Xilinx ISE WebPACK 12.2

Installer for Linux TAR/GZ 3.02GB (nepieciešams reģistrēties www.xilinx.com)

Installer for Windows TAR/GZ 2.96GB (nepieciešams reģistrēties www.xilinx.com)

ISE Design Suite 12: Installation, Licensing, and Release Notes PDF 1.44MB

Xilinx ISE WebPACK 12.2 on Ubuntu 10.04 LTS

Xilinx JTAG tools on Linux without proprietary kernel modules

ISE In-Depth Tutorial PDF 5.04MB

ISE Design Suite: Logic Edition – A Quick Tour WMV 47.50MB

ISim User Guide PDF 1.96MB

How to Use the ISE Simulator (ISim) WMV 40.90MB

Xilinx Spartan-3E

Xilinx Spartan-3E FPGA Starter Kit Board User Guide PDF 7.34MB
Spartan-3E Libraries Guide for Schematic Designs PDF 9.19MB
Spartan-3E Libraries Guide for HDL Designs PDF 3.94MB

Video applications using FPGA

FPGA Pong by Steve Chamberlin
Pong Game by Jean P. Nicolle

HDL tutorials

Verilog Tutorial I (10 pages) PDF 69.58KB
Verilog Tutorial II (227 pages) PDF 876.25KB
VHDL Tutorial I (15 pages)
VHDL Tutorial II (84 pages) PDF 391.95KB

@@ Line 40: / Line 40: @@
 |-
 | 24.09.2010
-| Trigeri. Pulkstenis.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L03-Triggers&Clock.1.02.pdf Trigeri. Pulkstenis.]
+Praktiskais darbs [[DIPb10:PD3 | PD3]].
+Mājas darbs [[DIPb10:MD3 | MD3]], termiņš 01.10.2010 08:30
 |-
 | 01.10.2010
-| CPU. DataPath. ALU.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L04-CPUPartOne.1.01.pdf CPU. DataPath. ALU.]
+Praktiskais darbs [[DIPb10:PD4 | PD4]].
+Mājas darbs [[DIPb10:MD4 | MD4]], termiņš 08.10.2010 08:30
 |-
 | 08.10.2010
-| CPU. DataPath (turpinājums). Instrukciju izpildes maģistrāle.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L05-CPUPartTwo.1.01.pdf CPU. DataPath (turpinājums). Instrukciju izpildes maģistrāle.]
+Praktiskais darbs [[DIPb10:PD5 | PD5]].
+Kursa projekts [[DIPb10:KP1 | KP1]], termiņš 1. daļai - 15.10.2010 12:10, 2. daļai - 22.10.2010 12:10
 |-
 | 15.10.2010
-| CPU. DataPath (turpinājums). Zarošanās. Kontrole.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L06-CPUPartThree.1.02.pdf CPU. DataPath (turpinājums). Zarošanās. Kontrole.]
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP1 | KP1]].
 |-
 | 22.10.2010
-| CPU. DataPath (nobeigums). Ātrāks summators. Reģistru fails.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L07-CPUPartFour.1.02.pdf CPU. DataPath (nobeigums). Ātrāks summators. Reģistru fails.]
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP1 | KP1]].
 |-
 | 29.10.2010
-| Vidus semestra kontroldarbs
+| '''09:00 Vidus semestra kontroldarbs'''
+Kursa projekts [[DIPb10:KP2 | KP2]], termiņš - 12.11.2010 12:10
 |-
 | 05.11.2010
-| DLX procesors un instrukcijas.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L08-DLXProcessorAndInstructions.1.01.pdf DLX procesors un instrukcijas.]
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP2 | KP2]].
 |-
 | 12.11.2010
-| Aparatūras apraksta valodas. Verilog.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L09-HDLVerilog.1.01.pdf Aparatūras apraksta valodas. Verilog.]
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP2 | KP2]].
 |-
+| [http://www.likumi.lv/doc.php?id=203023 13.11.2010]
-| 19.11.2010
-| Aparatūras apraksta valodas. VHDL.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L10-HDLVHDL.1.02.pdf Aparatūras apraksta valodas. VHDL.]
+Kursa projekts [[DIPb10:KP3 | KP3]], termiņš specifikācijai - 26.11.2010, visam projektam - 14.01.2011
 |-
 | 26.11.2010
-| Atmiņa. Fiziskās realizācijas varianti.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L11-Memory.1.02.pdf Atmiņa. Fiziskās realizācijas varianti.]
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP3 | KP3]].
 |-
 | 03.12.2010
-| Daudztaktu procesors.
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L12-MulticycleCPU.1.01.pdf Daudztaktu procesors.]
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP3 | KP3]].
+[http://bear.ces.cwru.edu/eecs_318/eecs_318_7.pdf Multicycle CPU] PDF 455.60KB (lekciju slaidi no Case Western Reserve University)
 |-
 | 10.12.2010
-| Daudztaktu procesors (nobeigums).
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L13-MulticycleCPUPartTwo.1.02.pdf Daudztaktu procesors (nobeigums).]
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP3 | KP3]].
+[http://www.sdsc.edu/~allans/cs141/l11redo.pdf Designing a Pipelined CPU] PDF 116.22KB (lekciju slaidi no San Diego Supercomputer Center)
 |-
 | 17.12.2010
+| [http://jupiter.cs.fmf.lu.lv/kursi/dip/L14-FPGA.1.01.pdf FPGA.]
-| FPGA.
+Praktiskajos darbos turpinām strādāt pie kursa projekta [[DIPb10:KP3 | KP3]].
+[http://www.ppouyan.net/wp-content/uploads/2010/09/fpga.pdf How Does FPGA Work] PDF 1.06MB (lekciju slaidi no Lund University)
 |-
 | 24.12.2010 - 02.01.2011
 | Ziemassvētku un Jaungada brīvdienas
 |-
-| XX.01.2011
+| 07.01.2011
+| '''08:30 - 12:10 Konsultācijas'''
-| Konsultācijas (piektdienās)
 |-
-| XX.01.2011
+| 14.01.2011
-| Gala eksāmena kontroldarbs
+| '''09:30 - 10:15 Gala eksāmena kontroldarbs'''
 |-
-| XX.01.2011
+| 14.01.2011
-| Projektu prezentācijas - kursa noslēgums
+| '''10:30 - 11:15 Projektu prezentācijas - kursa noslēgums'''
 |-
 |}
@@ Line 96: / Line 127: @@
 * [[DIPb10:PD1 | PD1]]
 * [[DIPb10:PD2 | PD2]]
+* [[DIPb10:PD3 | PD3]]
+* [[DIPb10:PD4 | PD4]]
+* [[DIPb10:PD5 | PD5]]
 == Mājas darbi (MD) ==
@@ Line 101: / Line 135: @@
 * [[DIPb10:MD1 | MD1]]
 * [[DIPb10:MD2 | MD2]]
+* [[DIPb10:MD3 | MD3]]
+* [[DIPb10:MD4 | MD4]]
 == Kursa projekti (KP) ==
 * [[DIPb10:KP1 | KP1]]
+* [[DIPb10:KP2 | KP2]]
+* [[DIPb10:KP3 | KP3]]
 == Literatūra ==
@@ Line 120: / Line 157: @@
 * [http://www.xilinx.com Xilinx kompānijas (FPGA ražotājs) portāls]
+==== Digital design textbooks @ Digilent Inc.====
+* [http://www.digilentinc.com/Data/Textbooks/Intro_to_Digital_Design-Digilent-Verilog_Online.pdf Introduction to Digital Design - Verilog Edition] PDF 5.81MB
+* [http://www.digilentinc.com/Data/Textbooks/Intro_Digital_Design-Digilent-VHDL_Online.pdf Introduction to Digital Design - VHDL Edition] PDF 6.68MB
+* Real Digital - A hands-on approach to digital design
+** [http://www.digilentinc.com/classroom/realdigital/M1/RealDigital_Module_1.pdf Module 1: Introduction to Electronic Circuits] PDF 465.54KB
+** [http://www.digilentinc.com/classroom/realdigital/M2/RealDigital_Module_2.pdf Module 2: Introduction to Digilent's Digital Design Circuit Boards] PDF 65.94KB
+** [http://www.digilentinc.com/classroom/realdigital/M3/RealDigital_Module_3.pdf Module 3: Circuit Structure with an Introduction to CAD Tools] PDF 247.60KB
+** [http://www.digilentinc.com/classroom/realdigital/M4/RealDigital_Module_4.pdf Module 4: Logic Minimization] PDF 353.07KB
+** [http://www.digilentinc.com/classroom/realdigital/M5/RealDigital_Module_5.pdf Module 5: Introduction to VHDL] PDF 197.37KB
+** [http://www.digilentinc.com/classroom/realdigital/M6/RealDigital_Module_6.pdf Module 6: Combinational Circuit Blocks] PDF 244.46KB
+** [http://www.digilentinc.com/classroom/realdigital/M7/RealDigital_Module_7.pdf Module 7: Combinational Arithmetic Circuits] PDF 361.00KB
+** [http://www.digilentinc.com/classroom/realdigital/M8/RealDigital_Module_8.pdf Module 8: Signal Propagation Delays] PDF 126.77KB
+** [http://www.digilentinc.com/classroom/realdigital/M9/RealDigital_Module_9.pdf Module 9: Basic Memory Circuits] PDF 232.41KB
+** [http://www.digilentinc.com/classroom/realdigital/M10/RealDigital_Module_10.pdf Module 10: The Structural Design of Sequential Circuits] PDF 245.58KB
 ==== Xilinx ISE WebPACK 12.2 ====
@@ Line 135: / Line 188: @@
 * [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/ise_tutorial_ug695.pdf ISE In-Depth Tutorial] PDF 5.04MB
-* [https://xilinx.webex.com/ec0605l/eventcenter/recording/recordAction.do?theAction=poprecord&actname=%2Feventcenter%2Fframe%2Fg.do&apiname=lsr.php&renewticket=0&renewticket=0&actappname=ec0605l&entappname=url0107l&needFilter=false&&isurlact=true&entactname=%2FnbrRecordingURL.do&rID=31975327&rKey=B2CB97CBBB0026E3&recordID=31975327&rnd=7154034615&siteurl=xilinx&SP=EC&AT=pb&format=short ISE Design Suite: Logic Edition – A Quick Tour] WMV 47.5MB
+* [https://xilinx.webex.com/ec0605l/eventcenter/recording/recordAction.do?theAction=poprecord&actname=%2Feventcenter%2Fframe%2Fg.do&apiname=lsr.php&renewticket=0&renewticket=0&actappname=ec0605l&entappname=url0107l&needFilter=false&&isurlact=true&entactname=%2FnbrRecordingURL.do&rID=31975327&rKey=B2CB97CBBB0026E3&recordID=31975327&rnd=7154034615&siteurl=xilinx&SP=EC&AT=pb&format=short ISE Design Suite: Logic Edition – A Quick Tour] WMV 47.50MB
 * [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/plugin_ism.pdf ISim User Guide] PDF 1.96MB
-* [https://xilinx.webex.com/ec0605l/eventcenter/recording/recordAction.do;jsessionid=PHcmMMRfyPT41QMhMNm1ryhh2bK1LyX1bM8bnkS9Qp7qgTTCG2S9!1328041475?theAction=poprecord&actname=%2Feventcenter%2Fframe%2Fg.do&apiname=lsr.php&renewticket=0&renewticket=0&actappname=ec0605l&entappname=url0107l&needFilter=false&&isurlact=true&entactname=%2FnbrRecordingURL.do&rID=41800312&rKey=82ac13e94441c96c&recordID=41800312&rnd=5574793851&siteurl=xilinx&SP=EC&AT=pb&format=short How to Use the ISE Simulator (ISim)] WMV 40.9MB
+* [https://xilinx.webex.com/ec0605l/eventcenter/recording/recordAction.do;jsessionid=PHcmMMRfyPT41QMhMNm1ryhh2bK1LyX1bM8bnkS9Qp7qgTTCG2S9!1328041475?theAction=poprecord&actname=%2Feventcenter%2Fframe%2Fg.do&apiname=lsr.php&renewticket=0&renewticket=0&actappname=ec0605l&entappname=url0107l&needFilter=false&&isurlact=true&entactname=%2FnbrRecordingURL.do&rID=41800312&rKey=82ac13e94441c96c&recordID=41800312&rnd=5574793851&siteurl=xilinx&SP=EC&AT=pb&format=short How to Use the ISE Simulator (ISim)] WMV 40.90MB
 ==== Xilinx Spartan-3E ====
 * [http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf Xilinx Spartan-3E FPGA Starter Kit Board User Guide] PDF 7.34MB
+* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/spartan3e_scm.pdf Spartan-3E Libraries Guide for Schematic Designs] PDF 9.19MB
+* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/spartan3e_hdl.pdf Spartan-3E Libraries Guide for HDL Designs] PDF 3.94MB
 ==== Video applications using FPGA ====
@@ Line 149: / Line 204: @@
 * [http://www.stevechamberlin.com/cpu/2009/06/21/fpga-pong/ FPGA Pong] by Steve Chamberlin
 * [http://www.fpga4fun.com/PongGame.html Pong Game] by Jean P. Nicolle
+==== HDL tutorials ====
+* [http://www.eecs.harvard.edu/cs141/resources/verilog-tutorial.pdf Verilog Tutorial I (10 pages)] PDF 69.58KB
+* [http://www.ece.umd.edu/class/enee359a.S2008/verilog_tutorial.pdf Verilog Tutorial II (227 pages)] PDF 876.25KB
+* [http://www.gmvhdl.com/VHDL.html VHDL Tutorial I (15 pages)]
+* [http://lslwww.epfl.ch/pages/teaching/cours_lsl/sl_info/vhdl-tutorial.pdf VHDL Tutorial II (84 pages)] PDF 391.95KB

Difference between revisions of "LU-DIP-B10:index"

Latest revision as of 16:46, 17 December 2010

Contents

Ievads digitālajā projektēšanā

Kalendārs

Praktiskie darbi (PD)

Mājas darbi (MD)

Kursa projekti (KP)

Literatūra

Saites

Digital design textbooks @ Digilent Inc.

Xilinx ISE WebPACK 12.2

Xilinx Spartan-3E

Video applications using FPGA

HDL tutorials

Navigation menu

Personal tools

Namespaces

Variants

Views

More

Search

Navigation

Tools