Difference between revisions of "BITL MCU"

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[[#Assignments | Assignments]] |
[[#Assignments | Assignments]] |
[[#Resources | Resources]] |
[[#Resources | Resources]] |
[[#{{CURRENTDAY2}}.{{CURRENTMONTH}}.{{CURRENTYEAR}}. | Today <small>(if there is a class)</small>]]
[[#{{CURRENTDAY2}}.{{CURRENTMONTH}}.{{CURRENTYEAR}} | Today <small>(if there is a class)</small>]]
</big>
</big>

'''Course: Introduction to Processors'''
'''Course: Introduction to Processors'''
===Introduction===
The course is about low level hardware architecture of the computers and the programming at that level. In particular, we study ARM Assembly programming language and techniques while discussing the microprocessor resources and features that implement the instructions. The students learn how to develop a code in Assembly and what to consider when implementing efficient programs in higher level languages.


===Deliverables===

* All assignments are due by the end of the day on the due date, unless otherwise specified.



=Calendar=
=Calendar=
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Representation of non-negative numbers in hardware, registers and memory. Decimal, binary, octal, and hexadecimal systems. Converting between the systems.
Representation of non-negative numbers in hardware, registers and memory. Decimal, binary, octal, and hexadecimal systems. Converting between the systems.
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====08.09.2023====
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|<big>'''Two's complement'''</big>
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Representing negative numbers in hardware. Register size, and why it is important. Methods for encoding negative numbers: packed, signed, bias, one's complement and two's complement. Converting between the value and two's complement in binary and hexadecimal systems.



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|<big>'''Lab :: Quiz 1'''</big>
|<big>'''Lab :: Quiz 1'''</big>
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'''Lab'''

Practicing the conversion between the systems with different bases


'''Quiz 1'''
'''Quiz 1'''


Decimal, binary, octal and hexadecimal systems.
Decimal, binary, octal and hexadecimal systems.

'''Lab'''

Quiz review. Practicing the conversion between the systems with different bases


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{| width='100%' style='background-color:#ddd;'
{| width='100%' style='background-color:#ddd;'
|<big>'''Two's complement'''</big>
|<big>'''Processor architecture'''</big>
|}
|}
Architecture of a processor. Registers, register file, ALU, datapath. CISC vs. RISC architectures. x86 architecture as CISC representative. ARM architecture as RISC. Instruction encoding.
Representing negative numbers in hardware. Register size, and why it is important. Methods for encoding negative numbers: packed, signed, bias, one's complement and two's complement. Converting between the value and two's complement in binary and hexadecimal systems.


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|<big>'''Lab :: Quiz 2'''</big>
|<big>'''Lab :: Quiz 2'''</big>
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'''Lab'''

Exercises with the two's complement


'''Quiz 2'''
'''Quiz 2'''


Two's complement.
Two's complement.

'''Lab'''

Quiz review. Exercises with the two's complement


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{| width='100%' style='background-color:#ddd;'
{| width='100%' style='background-color:#ddd;'
|<big>'''Processor architecture'''</big>
|<big>'''Computing environment'''</big>
|}
|}
Environment and tools for compiling and debugging Assembly programs. Compiler, preprocessor, assembly, linker, loader, debugger. Cross-compilation and toolchains. Emulators and virtual machines.
Architecture of a processor. Registers, register file, ALU, datapath. CISC vs. RISC architectures. x86 architecture as CISC representative. ARM architecture as RISC. Instruction encoding.


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{| width='100%' style='background-color:#ddd;'
{| width='100%' style='background-color:#ddd;'
|<big>'''Computing environment'''</big>
|<big>'''ARM Assembly and arithmetic'''</big>
|}
|}
Introduction to ARM Assembly language and programming. Instruction types. Arithmetic instructions. MOV, ADD, SUB. MVN, ADC, SBC, RSB, RSC. Barrel Shifter.
Environment and tools for compiling and debugging Assembly programs. Compiler, preprocessor, assembly, linker, loader, debugger. Cross-compilation and toolchains. Emulators and virtual machines.


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* HW1 announced

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{| width='100%' style='background-color:#ddd;'
{| width='100%' style='background-color:#ddd;'
|<big>'''ARM Assembly and arithmetic'''</big>
|<big>'''Flow control and tests'''</big>
|}
|}
Flow control in Assembly. Branch instructions. B, BL, BX, BLX. Working directly with PC register. CPSR flags. Condition field. Bit operations. AND, ORR, EOR, BIC, shift and rotation. CMP, CMN, TST, TEQ. Fast flags and the S postfix.
Introduction to ARM Assembly language and programming. Instruction types. Arithmetic instructions. MOV, ADD, SUB. MVN, ADC, SBC, RSB, RSC. Barrel Shifter.


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{| width='100%' style='background-color:#ddd;'
{| width='100%' style='background-color:#ddd;'
|<big>'''Flow control and tests'''</big>
|<big>'''Memory instructions'''</big>
|}
|}
Reading and writing data to memory. Memory access instructions. STR, LDR, STRB, STRH, LDRB, LDRH, LDRSB, LDRSH. Addressing modes: offset, pre-indexed and post-indexed. Using barrel shifter with addressing. Data alignment in memory.
Flow control in Assembly. Branch instructions. B, BL, BX, BLX. Working directly with PC register. CPSR flags. Condition field. Bit operations. AND, ORR, EOR, BIC, shift and rotation. CMP, CMN, TST, TEQ. Fast flags and the S postfix.


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* '''Due''' '''HW1'''


* HW2 announced
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|<big>'''Lab :: Quiz 3'''</big>
|<big>'''Lab :: Quiz 3'''</big>
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'''Lab'''

'''Quiz 3'''
'''Quiz 3'''


Code comprehension.
Code comprehension.


'''Lab'''
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Quiz review.
* '''Due''' '''HW1''' - Arithmetic progression
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|<big>'''Memory instructions'''</big>
|<big>'''Calling subroutines and interfacing with C'''</big>
|}
|}
Variable types in C: static, automatic and dynamic. Calling subroutines and parameter passing conventions. Parameters and return value. Stack and registers. Saving the registers, the context. Loading and storing multiple registers: LDM, STM. Interfacing between Assembly and C.
Reading and writing data to memory. Memory access instructions. STR, LDR, STRB, STRH, LDRB, LDRH, LDRSB, LDRSH. Addressing modes: offset, pre-indexed and post-indexed. Using barrel shifter with addressing. Data alignment in memory.


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{| width='100%' style='background-color:#ddd;'
|<big>'''Calling subroutines and interfacing with C'''</big>
|<big>'''Symbols'''</big>
|}
|}
Symbol encoding in hardware and software. Code tables. ASCII. EBCDIC. ISO code tables. Foreign letter symbols. UTF-8, UTF-16. Strings in C and memory. Converting values to symbols and strings.
Variable types in C: static, automatic and dynamic. Calling subroutines and parameter passing conventions. Parameters and return value. Stack and registers. Saving the registers, the context. Loading and storing multiple registers: LDM, STM. Interfacing between Assembly and C.


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* '''Due''' '''HW2'''


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|<big>'''Lab'''</big>
|<big>'''Lab'''</big>
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Practice passing parameters and working with buffers.
TBD

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* '''Due''' '''HW2''' - Matrix multiplication


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|<big>'''Symbols'''</big>
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Symbol encoding in hardware and software. Code tables. ASCII. EBCDIC. ISO code tables. Foreign letter symbols. UTF-8, UTF-16. Strings in C and memory. Converting values to symbols and strings.


====03.11.2023====
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* '''Due''' '''M1P1''' - Midterm 1 programming task 1, tested
* '''Due''' '''M1P1''' - Midterm 1 programming task 1, tested
* '''Due''' '''M1P2''' - Midterm 1 programming task 2, tested
* '''Due''' '''M1P2''' - Midterm 1 programming task 2, tested
* Project announced

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|<big>'''Lab'''</big>
|<big>'''Lab'''</big>
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Midterm review.
TBD


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|<big>'''Lab'''</big>
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Lab. Q&A session

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Execution time for instructions. Case study for code optimization. Leveraging the documentation and specification of instructions. Reordering the code. Unrolling loops. Taking advantage of branch prediction. Cache memory and the code performance.
Execution time for instructions. Case study for code optimization. Leveraging the documentation and specification of instructions. Reordering the code. Unrolling loops. Taking advantage of branch prediction. Cache memory and the code performance.


Documentation: [http://download.intel.com/design/intelxscale/27347302.pdf Intel XScale R Core Developer’s Manual].
|


The section and focus:
* A.2.1.2 — Processor execution pipe diagram. Instruction and data flow description.
* 10.4 — Instruction execution time. For example, multiplication vs. addition.
* 5 — Branch prediction mechanism
* 4 and 6 — Cache memory. Instruction cache and Data cache.
* A.3–A.5 — Optimizations as suggested by Intel.

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Due: Choose the format of your exam: Project vs. Test.
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* '''Due By midnight''' '''Proj''' - Project


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|<big>'''Exam'''</big>
|<big>'''Exam'''</big>
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<!--
Data representation in memory.
Data representation in memory.
Assembly code comprehension.
Assembly code comprehension.
Multiple choice questions and a programming task.
Multiple choice questions and a programming task.
-->

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* All deliverables due
* '''Due''' '''ExamP1''' - Exam programming task, tested
<!--

* '''Due by midnight''' '''ExP1''' - Exam programming task, tested
* '''Due by midnight''' '''Proj''' - Project
-->
|}
|}


=Assignments=
=Assignments=
* Homework HW1 is available from e-Studijas
* Homeworks are available from e-Studijas





Latest revision as of 20:14, 5 October 2023

Shortcuts: Calendar | Assignments | Resources | Today (if there is a class)

Course: Introduction to Processors

Introduction

The course is about low level hardware architecture of the computers and the programming at that level. In particular, we study ARM Assembly programming language and techniques while discussing the microprocessor resources and features that implement the instructions. The students learn how to develop a code in Assembly and what to consider when implementing efficient programs in higher level languages.

Deliverables

  • All assignments are due by the end of the day on the due date, unless otherwise specified.

Calendar

Date Topic, content Deliverables

01.09.2023

9:00

Introduction

Microprocessors and microcontrollers. Applications. Architectures. Coourse outline.

01.09.2023

11:10

Hexadecimal arithmetic

Representation of non-negative numbers in hardware, registers and memory. Decimal, binary, octal, and hexadecimal systems. Converting between the systems.

08.09.2023

9:00

Two's complement

Representing negative numbers in hardware. Register size, and why it is important. Methods for encoding negative numbers: packed, signed, bias, one's complement and two's complement. Converting between the value and two's complement in binary and hexadecimal systems.


08.09.2023

11:10

Lab :: Quiz 1

Quiz 1

Decimal, binary, octal and hexadecimal systems.

Lab

Quiz review. Practicing the conversion between the systems with different bases


15.09.2023

9:00

Processor architecture

Architecture of a processor. Registers, register file, ALU, datapath. CISC vs. RISC architectures. x86 architecture as CISC representative. ARM architecture as RISC. Instruction encoding.

15.09.2023

11:10

Lab :: Quiz 2

Quiz 2

Two's complement.

Lab

Quiz review. Exercises with the two's complement


22.09.2023

9:00

Computing environment

Environment and tools for compiling and debugging Assembly programs. Compiler, preprocessor, assembly, linker, loader, debugger. Cross-compilation and toolchains. Emulators and virtual machines.

22.09.2023

11:10

Lab

Developing and testing a simple Assembly program. Using cross-compilation tools. Introduction to the Make system.


29.09.2023

9:00

ARM Assembly and arithmetic

Introduction to ARM Assembly language and programming. Instruction types. Arithmetic instructions. MOV, ADD, SUB. MVN, ADC, SBC, RSB, RSC. Barrel Shifter.

  • HW1 announced

29.09.2023

11:10

Lab

Advanced features of the Make system.

06.10.2023

9:00

Flow control and tests

Flow control in Assembly. Branch instructions. B, BL, BX, BLX. Working directly with PC register. CPSR flags. Condition field. Bit operations. AND, ORR, EOR, BIC, shift and rotation. CMP, CMN, TST, TEQ. Fast flags and the S postfix.

06.10.2023

11:10

Lab

Evaluating and following the code "on paper".


13.10.2023

9:00

Memory instructions

Reading and writing data to memory. Memory access instructions. STR, LDR, STRB, STRH, LDRB, LDRH, LDRSB, LDRSH. Addressing modes: offset, pre-indexed and post-indexed. Using barrel shifter with addressing. Data alignment in memory.

  • Due HW1
  • HW2 announced

13.10.2023

11:10

Lab :: Quiz 3

Quiz 3

Code comprehension.

Lab

Quiz review.

20.10.2023

9:00

Calling subroutines and interfacing with C

Variable types in C: static, automatic and dynamic. Calling subroutines and parameter passing conventions. Parameters and return value. Stack and registers. Saving the registers, the context. Loading and storing multiple registers: LDM, STM. Interfacing between Assembly and C.

20.10.2023

11:10

Lab

Debugging Assembly programs. Gnu debugger gdb.

27.10.2023

9:00

Symbols

Symbol encoding in hardware and software. Code tables. ASCII. EBCDIC. ISO code tables. Foreign letter symbols. UTF-8, UTF-16. Strings in C and memory. Converting values to symbols and strings.

  • Due HW2

27.10.2023

11:10

Lab

Practice passing parameters and working with buffers.

03.11.2023

9:00

Midterm

Data representation in memory. Assembly code comprehension. Two programming tasks.


10.11.2023

11:10

Expressions and Macro commands

Expressions in Assembly. Operators in expressions. Constants. Assigning values to symbols. Directives: .set, .equiv, .eqv. Conditional compilation. Directives .if, .ifdef, .endif., ifb, .ifc, .ifeqs. More conditionals .ifeq, .ifge, .ifne and others. Macro commands: .macro, .endm., .rept. Recursive macros. Local macros. Macros across sections.

  • Due M1P1 - Midterm 1 programming task 1, tested
  • Due M1P2 - Midterm 1 programming task 2, tested
  • Project announced

10.11.2023

11:10

Lab

Midterm review.

17.11.2023

9:00

Inline Assembly

Including Assembly in C code. Inline code and Assembly code operands. Tasks for the compiler, linker and loader. Dynamic loaders and libraries.

17.11.2023

11:10

Lab

Lab. Q&A session

24.11.2023

9:00

Optimizations

Execution time for instructions. Case study for code optimization. Leveraging the documentation and specification of instructions. Reordering the code. Unrolling loops. Taking advantage of branch prediction. Cache memory and the code performance.

Documentation: Intel XScale R Core Developer’s Manual.

The section and focus:

  • A.2.1.2 — Processor execution pipe diagram. Instruction and data flow description.
  • 10.4 — Instruction execution time. For example, multiplication vs. addition.
  • 5 — Branch prediction mechanism
  • 4 and 6 — Cache memory. Instruction cache and Data cache.
  • A.3–A.5 — Optimizations as suggested by Intel.

Due: Choose the format of your exam: Project vs. Test.

24.11.2023

11:10

Lab

Review of the course topics

11-21.12.2023

Exam week

Time for exams

15.12.2023

9:00

Exam
  • All deliverables due

Assignments

  • Homeworks are available from e-Studijas


Resources

Tutorials

Make

GDB

Remote debugging example

Debugging myprog with a parameter 10.

  • First, start the qemu emulator, providing the communications port (12345), and run it in background (&).
    • Before you do this, make sure that the port is not in use by anyone or anything.
  • Then start the gdb-multiarch with the name of the program and
  • Use the gdb command "remote target" with address (localhost) and the port (12345).
  • Finally start the program execution with "continue". Perhaps, you may want to set some breakpoints before that.
$ qemu-arm -L /usr/arm-linux-gnueabi -g 12345 myprog 10 &
$ gdb-multiarch myprog
    (gdb) target remote localhost:12345
    (gdb) continue

A few essential GDB commands

GDB command Shortcut Description
run Run the program from the beginning
continue c Continue (or start) the execution of the program
step s Execute the current line from the source. If there is a function call, step into it.

This command can have a parameter n that tells how many steps to make.

next n Execute the current line from the source. If there is a function call, stop after running it.

This command can have a parameter n that tells how many steps to make.

break <x> b <x>

Set a "breakpoint" to <x>, where <x> could be:

  • line_number in the current source code file
  • filename:line_number
  • function_name
  • filename:function_name
  • *address
  • ...and many others
list l Shows the source code (lines). Could be followed by a function_name or file:line_number
info registers i r Prints all registers and their values. Can be followed by one or more register names.
set step mode on Set running mode such that "step" will enter the code that has no debug information available.

Using "off" instead of "on" resets this mode.

ARM

Xscale

Insights